EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 449

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Channel Locations
Table 1–3. Number of Transceiver Channels and Transceiver Block Locations in Stratix IV GX Devices (Part 2 of 2)
February 2011 Altera Corporation
EP4SGX180KF40
EP4SGX230KF40
EP4SGX290KF40
EP4SGX290KF43
EP4SGX360KF40
EP4SGX360KF43
EP4SGX530KF40
EP4SGX290NF45
EP4SGX360NF45
EP4SGX530NF45
Device Member
Figure 1–2
Stratix IV GX device that has 8 or 16 transceiver channels.
Figure 1–2. Transceiver Channel, PLL, and PCIe Hard IP Block Locations with 8 and 16
Stratix IV GX Transceiver Channels
Total Number of
Transceiver
Channels
36
48
shows transceiver channel, PLL, and PCIe hard IP block locations in each
EP4SGX290FH29, EP4SGX360FH29, EP4SGX110FF35, EP4SGX180FF35,
EP4SGX230FF35, EP4SGX290FF35, EP4SGX360FF35
(16 transceivers)
Transceiver Block GXBL1
Transceiver Block GXBL0
Twelve regular transceiver channels supporting data rates between 600 Mbps
and 8.5 Gbps and six CMU channels supporting data rates between 600 Mbps
and 6.5 Gbps located in three transceiver blocks:
■
■
Refer to
Sixteen regular transceiver channels supporting data rates between 600 Mbps
and 8.5 Gbps and eight CMU channels supporting data rates between
600 Mbps and 6.5 Gbps located in four transceiver blocks:
■
■
Refer to
ATX PLL R0 (6G)
Right side—GXBR0, GXBR1, and GXBR2
Left side—GXBL0, GXBL1, and GXBL2
Right side—GXBR0, GXBR1, GXBR2, and GXBR3
Left side—GXBL0, GXBL1, GXBL2, and GXBL3
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Figure 1–3 on page
Figure 1–4 on page
Transceiver Channel Location
1–6.
1–7.
Transceiver Block GXBR1
Transceiver Block GXBR0
Stratix IV Device Handbook Volume 2: Transceivers
EP4SGX70DF29
EP4SGX110DF29
EP4SGX180DF29
EP4SGX230DF29
(8 transceivers)
ATX PLL R0 (6G)
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
1–5