EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 514
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Price
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Manufacturer:
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325
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SHARP
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ALTERA
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490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (32Mb)
1–70
Table 1–31. Word Aligner Options Available in Basic Single-Width and Double-Width Modes
Stratix IV Device Handbook Volume 2: Transceivers
Basic
Double-
Width
Note to
(1) For more information about word aligner operation, refer to
Functional
Mode
Width Mode” on page
Table
1–31:
20-bit
PMA-PCS
Interface
Width
16-bit
1–66.
Word Alignment
Alignment
Alignment
Manual
Bit-Slip
Manual
Bit-Slip
Mode
8-, 16-, and
8-, 16-, and
7-, 10-, and
7-, 10-, and
Alignment
Pattern
Length
32-bit
32-bit
20-bit
20-bit
Word
“Word Aligner in Single-Width Mode” on page 1–60
rx_enapatternalign
Rising Edge
Rising Edge
Sensitivity
Sensitive
Sensitive
N/A
N/A
Chapter 1: Transceiver Architecture in Stratix IV Devices
Stays high after
the word aligner
aligns to the
word alignment
pattern. Goes low
on receiving a
rising edge on
rx_enapattern
align until a
new word
alignment pattern
is received.
Stays high after
the word aligner
aligns to the
word alignment
pattern. Goes low
on receiving a
rising edge on
rx_enapattern
align until a
new word
alignment pattern
is received.
rx_syncstatus
Behavior
N/A
N/A
February 2011 Altera Corporation
(Note 1)
Transceiver Block Architecture
and
“Word Aligner in Double-
(Part 2 of 2)
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
rx_patterndetect
Behavior
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