EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1007

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–14. MegaWizard Plug-In Manager Options (Protocol Settings —GIGE and XAUI) (Part 3 of 3)
Table 1–15. MegaWizard Plug-In Manager Options (Protocol Settings - [OIF] CEI PHY Interface)
February 2011 Altera Corporation
Enable transmitter bit reversal.
What is the word alignment pattern
length?
Enable run-length violation checking
with a run length of __.
Protocol Settings Screen for the (OIF) CEI Phy Interface
ALTGX Setting
ALTGX Setting
Table 1–15
Protocol Settings screen of the MegaWizard Plug-In Manager for your ALTGX custom
megafunction variation.
lists the available options for the (OIF) CEI Phy Interface mode in the
Enabling this option reverses every bit of the
10-bit parallel data at the input of the serializer.
The 10-bit input to the serializer D[9:0] is
reversed to D[0:9].
This option sets the word alignment pattern
length. The available choices are 7 and 10 for the
GIGE and XAUI modes. The default setting for this
option is 10.
This option creates the output signal rx_rlv.
Enabling this option also activates the run-length
violation circuit. If the number of continuous 1s and
0s exceeds the number that you set in this option,
the run-length violation circuit asserts the rx_rlv
signal. The rx_rlv signal is asynchronous to the
receiver data path and is asserted for a minimum of
two recovered clock cycles.
For a 32-bit channel width, the run length limits are
8 to 512 in increments of eight.
Description
Description
“8B/10B Encoder” section in the
Transceiver Architecture in
Stratix IV Devices
“Rate Match (Clock Rate
Compensation) FIFO” section in
the
Stratix IV Devices
Stratix IV Device Handbook Volume 3
“Programmable Run Length
Violation Detection” section in
the
in Stratix IV Devices
Transceiver Architecture in
Transceiver Architecture
Reference
Reference
chapter.
chapter.
chapter.
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