EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 579

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–111. Compliance Pattern Transmission Support, 8-Bit Channel Width Configurations
Figure 1–112. Compliance Pattern Transmission Support, 16-Bit Wide Channel Configurations
February 2011 Altera Corporation
tx_forcedispcompliance
tx_forcedispcompliance[1:0]
tx_datain[7:0]
tx_ctrlenable[1:0]
tx_ctrlenable
tx_datain[15:0]
The PCIe protocol requires the first /K28.5/ code group of the compliance pattern to
be encoded with negative current disparity. To satisfy this requirement, the PCIe
interface block provides the input signal tx_forcedispcompliance. A high level on
tx_forcedispcompliance forces the associated parallel transmitter data on the
tx_datain port to transmit with negative current running disparity.
■
■
Figure 1–111
tx_forcedispcompliance signal while transmitting the compliance pattern in 8-bit
and 16-bit channel width configurations, respectively.
The PCIe specification defines four power states—P0, P0s, P1, and P2—that the
physical layer device must support to minimize power consumption.
■
■
For 8-bit transceiver channel width configurations, you must drive
tx_forcedispcompliance high in the same parallel clock cycle as the first /K28.5/
of the compliance pattern on the tx_datain port.
For 16-bit transceiver channel width configurations, you must drive only the LSB
of tx_forcedispcompliance[1:0] high in the same parallel clock cycle as
/K28.5/D21.5/ of the compliance pattern on the tx_datain port.
P0 is the normal operating state during which packet data is transferred on the
PCIe link.
P0s, P1, and P2 are low-power states into which the physical layer must transition
as directed by the PHY-MAC layer to minimize power consumption.
Power State Management
K28.5
BC
and
/K28.5/D21.5/
B5BC
Figure 1–112
01
D21.5
B5
K28.5
BC
show the required level on the
/K28.5/D10.2/
BC4A
00
D10.2
4A
01
K28.5
BC
/K28.5/D21.5/
Stratix IV Device Handbook Volume 2: Transceivers
B5BC
D21.5
B5
K28.5
BC
/K28.5/D10.2/
BC4A
D10.2
4A
1–135