EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 283

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Channels
Table 8–1. LVDS Channels Supported in Stratix IV E Device Row I/O Banks
Table 8–2. LVDS Channels Supported in Stratix IV E Device Column I/O Banks
February 2011 Altera Corporation
Notes to
(1) Receiver (Rx) = true LVDS input buffers with OCT R
(2) The LVDS Rx and Tx channels are equally divided between the left and right sides of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
(4) EP4SE360 devices are offered in the H780 package instead of the F780 package.
(5) EP4SE530 devices are offered in the H1152 package instead of the F1152 package.
(6) EP4SE530 devices are offered in the H1517 package instead of the F1517 package.
Notes to
(1) Rx = true LVDS input buffers without OCT R
(2) The LVDS Rx and Tx channels are equally divided between the top and bottom sides of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
(4) EP4SE360 devices are offered in the H780 package instead of the F780 package.
(5) EP4SE530 devices are offered in the H1152 package instead of the F1152 package.
(6) EP4SE530 devices are offered in the H1517 package instead of the F1517 package.
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4SE230
EP4SE360
EP4SE530
EP4SE820
LVDS_E_1R or LVDS_E_3R).
Device
Device
Table
Table
8–1:
8–2:
780-Pin FineLine BGA
64 Rx or eTx + 64 eTx
64 Rx or eTx + 64 eTx
780-Pin FineLine BGA
56 Rx or eTx + 56 Tx
56 Rx or eTx + 56 Tx
Table 8–1
supported in Stratix IV E devices. You can design the LVDS I/Os as true LVDS buffers
or emulated LVDS buffers, as long as the combination of the two do not exceed the
maximum count.
For example, there are a total of 112 LVDS pairs on row I/Os in the 780-pin EP4SE230
device (refer to
buffers and 56 true LVDS output buffers, or up to a maximum of 112 emulated LVDS
output buffers. For the 780-pin EP4SE230 device (refer to
of 128 LVDS pairs on column I/Os. You can design up to a maximum of 64 true LVDS
input buffers and 64 emulated LVDS output buffers, or up to a maximum of 128
emulated LVDS output buffers.
or eTx
or eTx
(4)
—
—
—
—
(4)
and
Table 8–2
D
Table
, eTx = emulated LVDS output buffers (either LVDS_E_1R or LVDS_E_3R).
1152-Pin FineLine BGA
1152-Pin FineLine BGA
96 Rx or eTx + 96 eTx
96 Rx or eTx + 96 eTx
96 Rx or eTx + 96 eTx
88 Rx or eTx + 88 Tx
88 Rx or eTx + 88 Tx
88 Rx or eTx + 88 Tx
D
, Transmitter (Tx) = true LVDS output buffers, eTx = emulated LVDS output buffers (either
8–1). You can design up to a maximum of 56 true LVDS input
list the maximum number of row and column LVDS I/Os
or eTx
or eTx
or eTx
—
(5)
—
(5)
128 Rx or eTx + 128 eTx
128 Rx or eTx + 128 eTx 144 Rx or eTx + 144 eTx
1517-Pin FineLine BGA
1517-Pin FineLine BGA
112 Rx or eTx + 112 Tx
112 Rx or eTx + 112 Tx
(Note
or eTx
(Note
or eTx
—
—
(6)
1), (2),
—
—
1), (2),
(6)
Table
(3)
Stratix IV Device Handbook Volume 1
(3)
8–2), there are a total
128 Rx or eTx + 128 eTx
1760-Pin FineLine BGA
1760- Pin FineLine BGA
112 Rx or eTx + 112 Tx
132 Rx or eTx + 132 Tx
or eTx
or eTx
—
—
—
—
8–5