EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 478

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–34
Stratix IV Device Handbook Volume 2: Transceivers
Transmitter Output Buffer
The Stratix IV GX and GT transmitter buffers are architecturally similar to each other.
They both support programmable output differential voltage (V
and on-chip termination (OCT) settings.
The transmitter buffer power supply only provides voltage to the transmitter output
buffers in the transceiver channels. The transmitter output buffer, shown in
Figure
programmable three-tap pre-emphasis circuit, internal termination circuitry, and
receiver detect capability to support PCIe functional mode.
Figure 1–31. Transmitter Output Buffer
Table 1–13
Stratix IV GX and GT devices, respectively.
Table 1–13. Supported Settings for the Stratix IV GX Transmitter Buffer
Table 1–14. Supported Settings for the Stratix IV GT Transmitter Buffer
Data rate
Transmitter buffer power (V
Transmitter buffer I/O standard
Transmitter buffer V
Data rate
Transmitter buffer power (V
Transmitter buffer I/O standard
Transmitter buffer V
1–31, has additional circuitry to improve signal integrity, such as V
and
Programmable
Table 1–14
Pre-emphasis
Parameter
Parameter
and V
CM
CM
OD
CCH_GXBL/Rn
CCH_GXBL/Rn
list the supported settings of the transmitter buffers in the
Receiver
Detect
)
)
42.5Ω,
42.5Ω,
+VTT-
Chapter 1: Transceiver Architecture in Stratix IV Devices
50 Ω
50 Ω
1.4-V and 1.5-V pseudo current mode logic
, 60 , 75
, 60 , 75
Ω
600 Mbps to 8.5 Gbps (1.4 V)
600 Mbps to 6.5 Gbps (1.5 V)
Ω
Transmitter Output Pins
600 Mbps—11.3 Gbps
Ω
Ω
1.4 V or 1.5 V
1.4-V PCML
February 2011 Altera Corporation
(PCML)
Setting
Setting
0.65 V
0.65 V
1.4 V
Transceiver Block Architecture
OD
), pre-emphasis,
OD
,