EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 559
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H40I3
Manufacturer:
ALTERA
Quantity:
325
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
SHARP
Quantity:
1 200
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA
Quantity:
490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 559 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–96. Transceiver Configurations in Basic Single-Width Mode with a 10-Bit PMA-PCS Interface for Stratix IV GX
Devices
Note to
(1) The maximum data rate specification shown in
February 2011 Altera Corporation
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
other speed grades offered, refer to the
TX PCS Latency
Interface Frequency
RX PCS Latency
(1)
(1)
Figure
FPGA Fabric
Interface Frequency
Interface Frequency
Data Rate (Gbps)
Low-Latency PCS
Rate Match FIFO
Fabric-Transceiver
Data Rate (Gbps)
Encoder/Decoder
Channel Bonding
(Pattern Length)
Fabric-Transceiver
Interface Width
Byte Ordering
FPGA Fabric -
Interface Width
Word Aligner
Interface Width
Byte SerDes
Transceiver
PMA-PCS
PMA-PCS
Functional
8B/10B
FPGA
(MHz)
FPGA
Modes
1–96:
Disabled
Disabled
8-Bit
10-Bit
0.6 -
9 - 11
Figure 1–96
single-width functional mode with a 10-bit PMA-PCS interface.
Figure 1–97
single-width functional mode with a 10-bit PMA-PCS interface.
60 -
250
5 - 6
2.5
Disabled
Disabled
Single
Width
Disabled
Enabled
Manual Alignment
10-Bit
187.5
4 - 5.5
20-Bit
0.6 -
30 -
6 - 8
3.75
(7-Bit, 10-Bit)
Basic
16-Bit
Disabled
Disabled
8-Bit
9 - 11
0.6 -
60 -
250
5 - 6
2.5
Double
Disabled
Enabled
Width
DC and Switching Characteristics
shows Stratix IV GX transceiver configurations allowed in Basic
shows Stratix IV GT transceiver configurations allowed in Basic
Stratix IV GX Configurations
Disabled
20-Bit
Enabled
4 - 5.5
16-Bit
187.5
0.6 -
3.75
30 -
6 - 8
Figure 1–96
Disabled
Disabled
10-Bit
0.6 -
9 - 11
60 -
250
5 - 6
2.5
10-Bit
Disabled
Disabled
PIPE
Disabled Disabled
Enabled
(7-Bit, 10-Bit)
187.5
20-Bit
4 - 5.5
0.6 -
30 -
10-Bit
3.75
XAUI
6 - 8
Disabled
Bit-Slip
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
Disabled
GIGE
10-Bit
0.6 -
8-Bit
9 - 11
60 -
250
5 - 6
2.5
Disabled
Enabled
Protocol
SRIO
10-Bit
Enabled
Disabled
16-Bit
187.5
0.6 -
4 - 5
3.75
30 -
6 - 8
SONET
/SDH
8-Bit
Disabled
Disabled
10-Bit
9 - 11
0.6 -
60 -
250
5 - 6
chapter.
2.5
Disabled
Disabled
Basic Single-Width
10-Bit PMA-PCS
Interface Width
16-Bit
(OIF)
CEI
0.6 - 3.75
Disabled
x1, x4, x8
Enabled Disabled
4 - 5.5
0.6 -
20-Bit
187.5
3.75
30 -
6 - 8
Synchronization
State Machine
10-Bit
(7-Bit, 10-Bit)
SDI
Automatic
Disabled Disabled
0.6 -
8-Bit
2.5
9 - 11
60 -
250
5 - 6
10-Bit
Disabled
Deterministic
Latency
16-Bit
Stratix IV Device Handbook Volume 2: Transceivers
187.5
4 - 5.5
30 -
6 - 8
Enabled
20-Bit
0.6 -
3.75
Enabled
Enabled
16-Bit
4 - 5.5
187.5
30 -
6 - 8
Disabled
Disabled
0.6 -
8-Bit
2.5
60 -
5 - 6
250
20 -
Enabled
24
Enabled
Disabled
16-Bit
0.6 -
187.5
4 - 5.5
3.75
11.5 -
30 -
14.5
Disabled
Disabled
10-Bit
0.6 -
2.5
4 - 5
Disabled
Disabled
Disabled
60 -
250
3 - 4
Enabled
Enabled
Disabled
0.6 -
20-Bit
4 - 5.5
3.75
187.5
3 - 4. 5
30 -
1–115
Related parts for EP4SE530H40I3
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: