EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 269
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
February 2011 Altera Corporation
Dynamic On-Chip Termination Control
f
f
1
The ALTMEMPHY megafunction dynamically calibrates the alignment for read- and
write-leveling during the initialization process.
For more information about the ALTMEMPHY megafunction, refer to the
Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User
Figure 7–30
needed to dynamically turn on OCT RT during a read and turn OCT RT off during a
write.
For more information about dynamic on-chip termination control, refer to the
Features in Stratix IV Devices
Figure 7–30. Stratix IV Dynamic OCT Control Block
Note to
(1) The write clock comes from either the PLL or the write-leveling delay chain.
Figure
7–30:
shows the dynamic OCT control block. The block includes all the registers
OCT Control Path
OCT Control
OCT Half-
Rate Clock
chapter.
2
HDR
Block
DFF
Write
Clock (1)
Resynchronization
Registers
DFF
OCT Enable
Stratix IV Device Handbook Volume 1
Guide.
External
I/O
7–49
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