EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 567

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
Receiver Bit Slipping
The number of bits slipped in the receiver’s word aligner is given out on the
rx_bitslipboundaryselectout[4:0] output port. The information on this output
depends on your deserializer block width.
In single-width mode with 8/10-bit channel width, the number of bits slipped in the
receiver path is given out sequentially on this output. For example, if zero bits are
slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of
0(00000); if two bits are slipped, the output on rx_bitslipboundaryselectout[4:0]
shows a value of 2 (00010).
In double-width mode with 16/20-bit channel width, the output is 19 minus the
number of bits slipped. For example, if zero bits are slipped, the output on
rx_bitslipboundaryselectout[4:0] shows a value of 19 (10011); if two bits are
slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 17
(10001).
The information about the rx_bitslipboundaryselectout[4:0] output port helps in
calculating the latency through the receiver datapath. You can use the information on
rx_bitslipboundaryselectout[4:0] to set up the tx_bitslipboundaryselect[4:0]
appropriately to cancel out the latency uncertainty.
Receiver Phase Comp FIFO in Register Mode
To remove the latency uncertainty through the receiver’s phase compensation FIFO,
select the Enable the RX phase comp FIFO in register mode option in the ALTGX
MegaWizard Plug-In Manager. In register mode, the phase compensation FIFO acts as
a register and thereby removes the uncertainty in latency. The latency through the
phase compensation FIFO in register mode is one clock cycle.
This mode is available in:
■
■
Transmitter Phase Compensation FIFO in Register Mode
In register mode, the phase compensation FIFO acts as a register and thereby removes
the uncertainty in latency. The latency through the transmitter and receiver phase
compensation FIFO in register mode is one clock cycle.
CMU PLL Feedback
To implement deterministic latency functional mode, the phase relationship between
the low-speed parallel clock and CMU PLL input reference clock must be
deterministic. You can achieve this by selecting the Enable PLL phase frequency
detector (PFD) feedback to compensate latency uncertainty in Tx dataout and Tx
clkout paths relative to the reference clock option in the ALTGX MegaWizard
Plug-In Manager. By selecting this option, a feedback path is enabled that ensures a
deterministic relationship between the low-speed parallel clock and CMU PLL input
reference clock.
Basic single-width mode with 8-bit channel width and 8B/10B Encoder enabled or
10-bit channel width with 8B/10B disabled.
Basic double-width mode with 16-bit channel width and 8B/10B encoder enabled
or 20-bit channel width with 8B/10B disabled.
Stratix IV Device Handbook Volume 2: Transceivers
1–123