EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 673
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
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SIV52002-3.2
Figure 2–1. Clocking Architecture Overview
Stratix IV Device Handbook Volume 2: Transceivers
February 2011
February 2011
SIV52002-3.2
This chapter provides detailed information about the Stratix
architecture. For this chapter, the term “Stratix IV devices” includes both
Stratix IV GX and GT devices. Similarly, the term “Stratix IV transceivers” includes
both Stratix IV GX and GT transceivers.
The clocking architecture chapter is divided into three main sections:
■
■
■
Other sections in this chapter include:
Figure 2–1
FPGA
Fabric
“Input Reference Clocking” on page
provided to the clock multiplier unit (CMU)/auxiliary transmit phase-locked loop
(ATX PLL) to generate the clocks required for transceiver operation.
“Transceiver Channel Datapath Clocking” on page
architecture internal to the transceiver block.
“FPGA Fabric-Transceiver Interface Clocking” on page
clocking options available when interfacing the transceiver with the FPGA fabric.
■
■
■
“FPGA Fabric PLLs-Transceiver PLLs Cascading” on page 2–9
“Using the CMU/ATX PLL for Clocking User Logic in the FPGA Fabric” on
page 2–72
“Configuration Examples” on page 2–73
shows an overview of the clocking architecture.
FPGA Fabric-Transciever
Input Reference Clocks
Interface Clocks
2. Transceiver Clocking in Stratix IV
Transceivers
Transceiver Channel Datapath Clocks
CMU/ATX PLL
or CDR
Transceiver Channels
2–2—describes how the reference clock is
2–20—describes the clocking
2–51—describes the
®
IV transceiver clocking
Devices
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