EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 608

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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Figure 1–130. Rate Match Insertion in XAUI Mode
Stratix IV Device Handbook Volume 2: Transceivers
rx_rmfifodatainserted
datain[3]
datain[2]
datain[1]
datain[0]
dataout[3]
dataout[2]
dataout[1]
dataout[0]
Figure 1–130
columns are required to be inserted.
For more information, refer to
page
GIGE Mode
IEEE 802.3 defines the 1000 Base-X PHY as an intermediate, or transition, layer that
interfaces various physical media with the media access control (MAC) in a gigabit
ethernet system. It shields the MAC layer from the specific nature of the underlying
medium. The 1000 Base-X PHY is divided into three sub-layers:
■
■
■
The PCS sublayer interfaces with the MAC through the gigabit medium independent
interface (GMII). The 1000 Base-X PHY defines a physical interface data rate of
1 Gbps.
Physical coding sublayer
Physical media attachment
Physical medium dependent (PMD)
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1–77.
shows an example of rate match insertion in the case where two ||R||
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“Rate Match (Clock Rate Compensation) FIFO” on
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Chapter 1: Transceiver Architecture in Stratix IV Devices
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Second ||R||
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February 2011 Altera Corporation
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Transceiver Block Architecture
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