EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 627

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–150. Serial RapidIO Mode Datapath
February 2011 Altera Corporation
rx_coreclk[0]
tx_coreclk[0]
FPGA
Fabric
1
FPGA
Fabric-Transceiver
Interface Clock
It also defines two link widths—single-lane (1×) and bonded four-lane (4×) at each
line rate.
Stratix IV GX and GT transceivers support only single-lane (1×) configuration at all
three line rates. Four 1× channels configured in Serial RapidIO mode can be
instantiated to achieve a 4× Serial RapidIO link. The four transmitter channels in this
4× Serial RapidIO link are not bonded. The four receiver channels in this 4× Serial
RapidIO link do not have lane alignment or deskew capability.
Figure 1–150
RapidIO mode.
Stratix IV GX and GT transceivers, when configured in Serial RapidIO functional
mode, provide the following PCS and PMA functions:
■
■
■
■
■
Stratix IV GX and GT transceivers do not have built-in support for other PCS
functions; for example, pseudo-random idle sequence generation and lane alignment
in 4× mode. Depending on your system requirements, you must implement these
functions in the logic array or external circuits.
8B/10B encoding/decoding
Word alignment
Lane synchronization state machine
Clock recovery from the encoded data
Serialization/deserialization
Compensation
tx_clkout[0]
RX Phase
FIFO
Compensation
wrclk rdclk
TX Phase
FIFO
shows the ALTGX transceiver datapath when configured in Serial
Serializer
Byte
De-
/2
8B/10B
8B/10B
Decoder
Decoder
Serializer
Byte
/2 /2
Transmitter Channel PCS
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Receiver Channel PCS
Match
FIFO
Rate
8B/10B
Encoder
Parallel Recovered Clock
Aligner
Word
Stratix IV Device Handbook Volume 2: Transceivers
Serializer
Receiver Channel PMA
Serializer
Transmitter Channel PMA
De-
De-
Serializer
Clock Divider
Local
CDR
High-Speed Serial Clock
1–183