EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 778

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–24
Table 3–8. PCIe Hard IP Block Restrictions When Combining Transceiver Channels with Different Functional and/or
Protocol Modes (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
Compiler MegaWizard Plug-In Manager)
Width
Link
Options Enabled in the PCI Express
×1
×4
PCIe Configuration (PCIe hard IP
Combining Channels Configured in Deterministic Latency Mode
Combining Channels Using the PCIe hard IP Block with Other Channels
(Data Interface
f
1
Width)
64-bit
64-bit
Lane
(3)
The ALTGX MegaWizard Plug-In Manager provides Deterministic Latency mode
with two variations (×1 and ×4) to eliminate uncertainty in the transceiver data path.
This functional mode provides the Enable Phase Frequency Detector (PFD) feed
back … option in the PLL/Ports screen. If you select this option for ×1, the low-speed
parallel clock from the transmitter serializer is fed back to the PFD input of the CMU
PLL; for ×4, the output of the low-speed parallel clock from the central clock divider is
provided as feed back.
For the ×1 variation, one CMU PLL is required for each transmitter channel in the
instance. As a result, in ×1 mode, you can configure only two channels within the
transceiver block in this mode. The restrictions for Deterministic Latency mode in ×4
mode are the same as that of the bonded x4 functional mode. For more information,
refer to
The Stratix IV GX and GT device contains an embedded PCIe hard IP block that
performs the phyMAC, datalink, and transaction layer functionality specified by PCIe
base specification 2.0. Each PCIe hard IP block is shared by two transceiver blocks.
The PCI Express Compiler Wizard provides you the options to configure the PCIe
hard IP block. When enabled, the transceiver channels associated with this block are
also enabled.
There are restrictions on combining transceiver channels with different functional
and/or protocol modes (for example, Basic mode) within two contiguous transceiver
blocks with the channels that use the PCIe hard IP block. The restrictions depend on
the number of channels used (×1 or ×4) and the number of virtual channels (VCs)
selected in the PCI Express Compiler MegaWizard Plug-In Manager.
the restrictions.
When you use the PCIe hard IP block, there are placement restrictions on the locations
of the transceiver channels.
For these channel placement restrictions, refer to the
(Note
Channel
“Bonded ×4 Functional Mode” on page
Virtual
(VC)
1
2
1
2
1), (2),
Ch0
PCIe ×1
PCIe ×1
(7)
(6)
Transceiver Block 0
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Avail.
Ch1
—
PCIe ×4
PCIe ×4
Avail.
Ch2
—
Combining Channels Configured in Protocol Functional Modes
(4)
Avail.
Ch3
—
3–17.
PCI Express Compiler User
Avail.
Avail.
Avail.
Avail.
Ch4
Transceiver Block 1
February 2011 Altera Corporation
Avail.
Avail.
Avail.
Avail.
Ch5
Table 3–8
Avail.
Avail.
Avail.
Avail.
Ch6
(5)
Guide.
lists
Avail.
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Avail.
Avail.
Ch7