EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 931

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Controller Port List
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 10 of 13)
February 2011 Altera Corporation
Transceiver Channel Reconfiguration Control/Status Signals
reconfig_mode_sel[3:0]
reconfig_address_out[5:0]
reconfig_address_en
reset_reconfig_address
Port Name
Output
Output
Output
Input/
Input
Input
Set the following values at this signal to activate the appropriate
dynamic reconfiguration mode:
3’b000 = PMA controls reconfiguration mode. This is the default
value.
3’b011 = data rate division in transmitter mode
3’b100 = CMU PLL reconfiguration mode
3’b101 = channel and CMU PLL reconfiguration mode
3’b110 = channel reconfiguration with transmitter PLL select mode
3’b111 = central control unit reconfiguration mode
The reconfig_mode_sel signal is 4 bits wide when you enable
Adaptive Equalization control or EyeQ control:
4'b1000 = AEQ control (continuous mode for a single channel)
4'b1001 = AEQ control (one time mode for a single channel)
4'b1010 = AEQ control (power down for a single channel)
4'b1011 = EyeQ control
reconfig_mode_sel[] is available as an input only when you
enable more than one dynamic reconfiguration mode.
This signal is always available for you to select in the Channel and
TX PLL reconfiguration screen. This signal is applicable only in the
dynamic reconfiguration modes grouped under the Channel and
TX PLL select/reconfig option.
This signal represents the current address used by the
ALTGX_RECONFIG instance when writing the .mif into the
transceiver channel. This signal increments by 1, from 0 to the last
address, then starts at 0 again. You can use this signal to indicate
the end of all the .mif write transactions
(reconfig_address_out[5:0] changes from the last address to
0 at the end of all the .mif write transactions).
This is an optional signal you can select in the Channel and TX PLL
reconfiguration screen. This signal is applicable only in dynamic
reconfiguration modes grouped under the Channel and TX PLL
select/reconfig option.
The dynamic reconfiguration controller asserts
reconfig_address_en to indicate that
reconfig_address_out[5:0] has changed. This signal is
asserted only after the dynamic reconfiguration controller
completes writing one 16-bit word of the .mif.
This is an optional signal you can select in the Channel and TX PLL
reconfiguration screen. This signal is applicable only in dynamic
reconfiguration modes grouped under the Channel and TX PLL
select/reconfig option.
Enable this signal and assert it for one reconfig_clk clock cycle if
you want to reset the reconfiguration address used by the
ALTGX_RECONFIG instance during reconfiguration.
Stratix IV Device Handbook Volume 2: Transceivers
Description
(Note
3),
(4)
5–85