EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 128
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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5–12
Table 5–3. Clock Input Pin Connectivity to the RCLK Networks (Part 2 of 2)
Table 5–4. Device PLLs and PLL Clock Pin Drivers
Stratix IV Device Handbook Volume 1
RCLK [34, 40]
RCLK [33, 37, 39, 43]
RCLK [32, 36, 38, 42]
RCLK [47, 51, 57, 61]
RCLK [46, 50, 56, 60]
RCLK [45, 49, 53, 55,
59, 63]
RCLK [44, 48, 52, 54,
58, 62]
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
Notes to
(1) For single-ended clock inputs, only the CLK<#>p pin has a dedicated connection to the PLL. If you use the CLK<#>n pin, a global clock is used.
(2) For the availability of the clock input pins in each device density, refer to the “Stratix IV Device Pin-Out Files” section of the
(3) These are non-compensated clock input paths. For the compensated input for these PLLs, use the corresponding PLL_[L, R][1,4]_CLK input
Dedicated Clock
CLK (p/n Pins)
Altera Devices
pin.
Input Pin
Clock Resource
Table
Clock Input Connections to the PLLs
5–4:
site.
Table 5–4
L1
—
—
—
—
—
—
—
—
—
—
—
—
v
v
v
v
(3)
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
L2
v
v
v
v
lists the dedicated clock input pin connectivity to Stratix IV PLLs.
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
L3
v
v
v
v
—
—
—
—
—
—
—
2
L4
—
—
—
—
—
—
—
3
—
—
—
—
—
—
—
—
—
—
—
—
v
v
v
v
(3)
(Note
—
—
—
—
—
—
—
4
1),
B1
—
—
—
—
v
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
(2)
—
—
—
—
—
—
—
PLL Number
B2
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
6
v
CLK (p/n Pins)
—
—
—
—
—
—
—
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
7
R1
—
—
—
—
—
—
—
—
—
—
—
—
v
v
v
v
(3)
—
—
—
—
—
—
—
8
R2
—
—
—
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
v
v
v
v
9
10
—
v
—
—
—
—
—
R3
—
—
—
—
—
—
—
—
—
—
—
—
Clock Networks in Stratix IV Devices
v
v
v
v
February 2011 Altera Corporation
11
—
—
v
—
—
—
—
R4
—
—
—
—
—
—
—
—
—
—
—
—
v
v
v
v
12
—
—
—
v
—
—
—
(3)
Pin-Out Files for
13
—
—
—
—
v
—
—
v
v
v
v
T1
—
—
—
—
—
—
—
—
—
—
—
—
v
14
—
—
—
—
—
—
v
v
v
v
T2
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
v
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