EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1022

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Architecture
February 2011 Altera Corporation
Dynamic Reconfiguration
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For more information about the ALTGX MegaWizard Plug-In Manager, refer to the
ALTGX Transceiver Setup Guide for Stratix IV Devices
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For more information about these restrictions, refer to the
Protocols and Data Rates in Stratix IV Devices
Use the Stratix IV transceivers in multiple-link interconnect environments by
dynamically reconfiguring the PMA controls (for example, V
Equalization, DC gain, and the transceiver channel configuration). You can also
reconfigure the PMA controls without affecting any other transceiver channel or the
logic in the FPGA fabric.
Use the transceiver channel reconfiguration to dynamically switch a transceiver
channel to multiple protocols and data rates. The Quartus II software allows you to
generate a memory initialization file (.mif) that stores unique transceiver settings and
provides a dynamic reconfiguration controller, which is soft logic that controls the
transceiver reconfiguration with minimal user interface logic. You can generate this
soft logic using the ALTGX_RECONFIG MegaWizard interface.
For more information about the ALTGX_RECONFIG interface, refer to the
ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices
All receiver channels in the Stratix IV GX device require offset cancellation to counter
offset variations in process, voltage, and temperature (PVT) on the receiver. The
dynamic reconfiguration controller initiates the sequence to perform offset
cancellation on the receiver channels. Therefore, if you configure the Stratix IV GX
transceiver channel in Receiver only or Transmitter and Receiver configuration, you
must instantiate a dynamic reconfiguration controller.
For more information about offset cancellation or dynamic reconfiguration of PMA
controls or channel configuration, refer to the “Offset Cancellation Feature” section in
the
In some configurations, specific functional blocks in the transceiver are disabled or
bypassed. Before you select a transceiver configuration, understand the functional
blocks that must be implemented in the FPGA fabric. For example, Basic (PMA
direct) mode provides reduced latency but does not have PCS functional blocks
enabled (for example, word aligner and 8B/10B encoder). Therefore, implement
these functional blocks in the FPGA fabric if you need them in your application.
Some examples of functional blocks that you may need to implement in the FPGA
fabric are shown in
Check whether the loopback features are available for your selected functional
mode. The Stratix IV GX transceiver provides diagnostic loopback features
between the transmitter channel and the receiver channel at the transceiver PCS
and PMA interfaces. These loopback features help in debugging your design.
If your design uses multiple transceiver channels within the same transceiver
block, based on the transceiver channel configurations, the Quartus
might impose restrictions on combining these channels.
Dynamic Reconfiguration in Stratix IV Devices
“Create Data Processing and Other User Logic” on page
chapter.
chapter.
chapter.
Configuring Multiple
Stratix IV Device Handbook Volume 3
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II software
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