EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 572
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Stratix IV Device Handbook Volume 2: Transceivers
PCIe Mode Configurations
Stratix IV GX and GT transceivers support both Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
data rates in PCIe functional mode. When configured for the Gen2 (5 Gbps) data rate,
the Stratix IV GX and GT transceivers allow dynamic switching between Gen2
(5 Gbps) and Gen1 (2.5 Gbps) signaling rates. Dynamic switch capability between the
two PCIe signaling rates is critical for speed negotiation during link training.
Stratix IV GX and GT transceivers support ×1, ×4, and ×8 lane configurations in PCIe
functional mode at both 2.5 Gbps and 5 Gbps data rates. In PCIe ×1 configuration, the
PCS and PMA blocks of each channel are clocked and reset independently. PCIe ×4
and ×8 configurations support channel bonding for four-lane and eight-lane PCIe
links. In these bonded channel configurations, the PCS and PMA blocks of all bonded
channels share common clock and reset signals.
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Block Architecture
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