EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 519

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–57. Receiver Byte Reversal Feature
February 2011 Altera Corporation
rx_revbyteordwa
The MSByte and LSByte of the input data to the transmitter may be erroneously
swapped. The receiver byte reversal feature is available to correct this situation.
An optional port, rx_revbyteordwa, is available only in Basic double-width mode to
enable receiver byte reversal. In 8B/10B enabled mode, a high value on
rx_revbyteordwa exchanges the 10-bit MSByte for the LSByte of the 20-bit word at the
output of the word aligner in the receiver datapath. In non-8B/10B enabled mode, a
high value on rx_revbyteordwa exchanges the 8-bit MSByte for the LSByte of the
16-bit word at the output of the word aligner in the receiver datapath. This
compensates for the erroneous exchanging at the transmitter and corrects the data
received by the downstream systems. rx_revbyteorderwa is a dynamic signal and can
cause an initial disparity error at the receiver of an 8B/10B encoded link. The
downstream system must be able to tolerate this disparity error.
Figure 1–57
Deskew FIFO
Code groups received across four lanes in a XAUI link can be misaligned with respect
to one another because of skew in the physical medium or differences between the
independent clock recoveries per lane. The XAUI protocol allows a maximum skew of
40 UI (12.8 ns) as seen at the receiver of the four lanes.
XAUI protocol requires the physical layer device to implement a deskew circuitry to
align all four channels. To enable the deskew circuitry at the receiver to align the four
channels, the transmitter sends a /A/ (/K28.3/) code group simultaneously on all
four channels during inter-packet gap (IPG). The skew introduced in the physical
medium and the receiver channels can cause the /A/ code groups to be received
misaligned.
Receiver Byte Reversal in Basic Double-Width Modes
MSByte
MSByte
MSByte
LSByte
LSByte
LSByte
shows the receiver byte reversal feature.
00
01
01
00
00
01
02
03
03
02
02
03
04
05
05
04
06
07
07
06
07
06
08
09
09
08
09
08
0A
0B
0B
0A
0B
0A
with rx_revbyteordwa
Word Aligner Output
Data without Receiver Byte
Reversal enabled
Data with Receiver Byte
Reversal enabled
Stratix IV Device Handbook Volume 2: Transceivers
asserted
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