HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 1004

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25 Electrical Characteristics
25.3.8
Table 25.9 Peripheral Module Signal Timing
Conditions: V
Note:
Rev. 4.00 Sep. 14, 2005 Page 954 of 982
REJ09B0023-0400
Module Item
SCIF
PORT
DMAC DREQ setup time
*
Input clock cycle (synchronous)
Input clock rising time
Input clock falling time
Input clock width
Transmit data delay time
(synchronous)
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
Output data delay time
Input data setup time
Input data hold time
DREQ hold time
DACK, TEND delay time
Peripheral Module Signal Timing
t
Pcyc
V
CC
SS
indicate Pclock cycle.
Q = 3.0 V to 3.6 V, V
= V
SCK
SS
Q = AV
(asynchronous)
Figure 25.42 SCK Input Clock Timing
SS
= 0 V, Ta = −40°C to +85°C
t
CC
SCKW
= 1.8 V ± 5%, AV
Symbol Min.
t
t
t
t
t
t
t
t
t
t
t
t
t
Scyc
SCKR
SCKF
SCKW
TXD
RXS
RXH
PORTD
PORTS2
PORTH2
DREQ
DREQH
DACD
16
4
—
—
0.4
—
4 t
100
—
100
100
8
8
—
Pcyc
t
SCKR
t
Scyc
+ 15 —
CC
= 3.0 V to 3.6 V,
Max.
—
—
1.5
1.5
0.6
3 t
—
100
—
—
—
—
12
t
Pcyc
SCKF
+ 15 ns
Unit
t
t
t
t
t
ns
ns
ns
ns
Pcyc
Pcyc
Pcyc
Pcyc
Scyc
Figure(s)
25.42
25.42
25.42
25.42
25.42
25.43
25.43
25.43
25.44
25.45
25.46