HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 800

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 20 USB Function Module
20.3.1
Together with USB interrupt flag registers 1 (USBIFR1) and 2 (USBIFR2), USBIFR0 indicates
interrupt status information required by the application. When an interrupt occurs, the
corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the
combination with USB interrupt enable register 0 (USBIER0). Clearing is performed by writing 0
to the bit to be cleared, and 1 to the other bits. However, EP1 FULL and EP2 EMPTY are status
bits, and cannot be cleared.
USBIFR0 is initialized to H'10 by a power-on reset.
Rev. 4.00 Sep. 14, 2005 Page 750 of 982
REJ09B0023-0400
Bit
7
6
5
4
3
USB Interrupt Flag Register 0 (USBIFR0)
Bit Name
BRST
EP1FULL
EP2TR
EP2EMPTY 1
SETUPTS
Initial
Value
0
0
0
0
R/W
R/W
R
R/W
R
R/W
Description
Bus Reset
Set to 1 when the bus reset signal is detected on the
USB bus.
EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data normally from the host, and holds a value of 1 as
long as there is valid data in the FIFO buffer. EP1
FULL is a status bit, and cannot be cleared.
EP2 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 2 is
received from the host. A NACK handshake is
returned to the host until data is written to the FIFO
buffer and packet transmission is enabled.
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written. EP2 EMPTY is a status bit, and cannot be
cleared.
Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives normally
a setup command requiring decoding on the
application side, and returns an ACK handshake to
the host.