HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 540

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 I
(Master output)
Rev. 4.00 Sep. 14, 2005 Page 490 of 982
REJ09B0023-0400
(Master output)
(Slave output)
processing
(Master output)
(Master output)
(Slave output)
ICDRS
ICDRT
TDRE
TEND
User
SDA
SDA
SCL
processing
ICDRS
SCL
SDA
SDA
ICDRT
TDRE
TEND
User
[2] Instruction of start
2
C Bus Interface 2 (IIC2)
condition issuance
[5] Write data to ICDRT
Figure 16.5 Master Transmit Mode Operation Timing (1)
Figure 16.6 Master Transmit Mode Operation Timing (2)
A
9
Bit 7
1
Bit 7
[3] Write data to ICDRT (first byte)
1
Bit 6
2
Bit 6
Address + R/W
2
Bit 5
3
Address + R/W
Slave address
Bit 5
3
Data n
Bit 4
4
Data n
Bit 4
Bit 3
4
5
Bit 3
Bit 2
5
6
[4] Write data to ICDRT (second byte)
Bit 1
Bit 2
7
6
[6] Issue stop condition. Clear TEND.
R/W
Bit 0
Bit 1
8
7
A
9
Bit 0
8
[7] Set slave receive mode
[5] Write data to ICDRT (third byte)
A/A
9
Data 1
Data 1
Bit 7
1
Bit 6
Data 2
2