HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 988

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 938 of 982
REJ09B0023-0400
A12/A11*
D31 to D0
A25 to A0
DACKn*
RASU/L
CASU/L
RD/WR
DQMxx
Figure 25.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
CKIO
CKE
CSn
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)
BS
1
2
Note:
t
t
t
t
CSD1
t
t
RWD1
DQMD1
AD1
RASD1
t
AD1
DACD
Tr
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
address
t
RASD1
Row
Trw
t
t
t
t
AD1
CASD1
AD1
BSD
Tc1
(High)
Read command
t
AD1
Tc2
address
Column
t
AD1
Td1
Tc3
t
RDS2
t
t
AD1
t
AD1
command
RDH2
Td2
Tc4
ReadA
(1 to 4)
t
t
t
CASD1
AD1
BSD
Td3
t
Td4
RDS2
t
t
t
CSD1
DQMD1
RDH2
t
DACD
Tde
t
t
AD1
RWD1