HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 39

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 20.16 EP2 PKTE Operation ............................................................................................ 785
Figure 20.17 Example of USB Function Module External Circuitry
Figure 20.18 Example of USB Function Module External Circuitry
Figure 20.19 IRQ0 and IRQ1 Interrupt Circuitry ....................................................................... 790
Figure 20.20 USB Standby Operation Timing ........................................................................... 790
Figure 20.21 Sample Flowchart for Initialization of the USB Bus Power Control Method ....... 791
Figure 20.22 Sample Flowchart for Changing the State from USB Suspend to Standby ........... 792
Figure 20.23 Sample Flowchart for AWAKE ............................................................................ 793
Figure 20.24 Timing for Setting the TR Interrupt Flag .............................................................. 796
Section 21 A/D Converter
Figure 21.1 Block Diagram of A/D Converter ........................................................................... 798
Figure 21.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 806
Figure 21.3 Example of A/D Converter Operation
Figure 21.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to
Figure 21.5 A/D Conversion Timing .......................................................................................... 811
Figure 21.6 Definitions of A/D Conversion Accuracy ............................................................... 814
Figure 21.7 Example of Analog Input Protection Circuit ........................................................... 817
Figure 21.8 Analog Input Pin Equivalent Circuit ....................................................................... 817
Figure 21.9 Example of Analog Input Circuit ............................................................................ 817
Section 22 Pin Function Controller (PFC)
Figure 22.1 Internal Block Diagram of I/O Buffer with Weak Keeper ...................................... 841
Figure 22.2 Internal Block Diagram of I/O Buffer with Open Drain ......................................... 842
Section 23 I/O Ports
Figure 23.1 Port A ...................................................................................................................... 843
Figure 23.2 Port B ...................................................................................................................... 845
Figure 23.3 Port C ...................................................................................................................... 847
Figure 23.4 Port D ...................................................................................................................... 849
Figure 23.5 Port E....................................................................................................................... 851
Figure 23.6 Port F ....................................................................................................................... 853
Figure 23.7 Port G ...................................................................................................................... 856
Figure 23.8 Internal Block Diagram of PG7DT to PG0DT ........................................................ 859
Figure 23.9 Port H ...................................................................................................................... 860
Figure 23.10 Port J...................................................................................................................... 862
(Multi Mode, Channels AN0 to AN2 Selected) ..................................................... 807
AN2 Selected) ........................................................................................................ 809
(For On-Chip Transceiver).................................................................................... 787
(For External Transceiver) .................................................................................... 788
Rev. 4.00 Sep. 14, 2005 Page xxxix of l