HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 245

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

8.4
The X/Y memory can be accessed by the DMAC via the I bus. Use the addresses
between H'05007000 and H'05008FFF or H'05017000 and H'05018FFF.
8.5
When accessing the X/Y memory from the CPU and DSP, if the cache is on, access must be
performed from space P2 (non-cacheable space). Operation during access from space P0 cannot be
guaranteed. When the cache is off, spaces P0 and P2 can both be used. Specify the P2 area for
parallel operation and double data transfer. (See section 3.1.9, Data Transfer Operation.)
8.6
In sleep mode, the X/Y memory is not accessed from the I bus master module such as DMAC.
8.7
When an address error in write access to the X/Y memory occur, the contents of the X/Y memory
may be corrupted.
X/Y Memory Access from DMAC
Usage Note
Sleep Mode
Address Error
Rev. 4.00 Sep. 14, 2005 Page 195 of 982
Section 8 X/Y Memory
REJ09B0023-0400