HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 396

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
Rev. 4.00 Sep. 14, 2005 Page 346 of 982
REJ09B0023-0400
BSZ
1, 0
11 (32 bits)
Output Pin of
This LSI
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Example of connected memory
64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 1
2. Bank address specification
access mode.
(4)-2
A2/3
ROW
1, 0
00 (11 bits)
Row Address
Output Cycle
A25
A24
A23
A22*
A21*
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
2
2
Setting
A2/3
COL
1, 0
00 (8 bits)
Column Address
Output Cycle
A17
A16
A15
A22*
A21*
A20
L/H*
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
2
SDRAM Pin
A13 (BA1)
A12 (BA0)
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
Unused
Specifies bank
Address
Specifies
address/precharge
Address
Unused