HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 294

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 User Break Controller (UBC)
11.2.2
BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address
specified by BARA.
11.2.3
Break bus cycle register A (BBRA) is a 16-bit readable/writable register, which specifies (1) L bus
cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in
the break conditions of channel A.
Rev. 4.00 Sep. 14, 2005 Page 244 of 982
REJ09B0023-0400
Bit
31 to 0
Bit
15 to 8
7
6
Break Address Mask Register A (BAMRA)
Break Bus Cycle Register A (BBRA)
Bit Name

CDA1
CDA0
Bit Name
BAMA31 to
BAMA0
Initial
Value
All 0
Initial
Value
All 0
0
0
R/W
R/W
R/W
R
R/W
R/W
Description
Break Address Mask A
Specify bits masked in the channel A break address
bits specified by BARA (BAA31 to BAA0).
0: Break address bit BAAn of channel A is included in
1: Break address bit BAAn of channel A is masked and
Note: n = 31 to 0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
L Bus Cycle/I Bus Cycle Select A
Select the L bus cycle or I bus cycle as the bus cycle
of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
the break condition
is not included in the break condition