HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 335

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
Bit
10
9
8 to 0
*
Bit Name
BSZ1
BSZ0

The CS0CR samples the external pins (MD3) that specify the bus width at power-on
reset.
Initial
Value
1*
1*
All 0
R/W
R/W
R/W
R
Description
Data Bus Size
Specify the data bus sizes of spaces.
The data bus sizes of areas 2, 3, 4 and 5A are shown
below.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
11: 32-bit size
For MPX-I/O, selects bus width by address
Notes: 1. If area 5B is specified as MPX-I/O, the bus
Reserved
These bits are always read as 0. The write value
should always be 0.
2. The data bus width for area 0 is specified by
3. If area 6 is specified as burst MPX-I/O, the
4. If area 2 or area 3 is specified as SDRAM
width can be specified as 8 bits or 16 bits by
the address according to the SZSEL bit in
CS5BWCR by specifying these bits to 11.
the external pin. The BSZ1 and BSZ0 bit
settings in the CS0BCR register are
ignored.
bus width can be specified as 32 bits only.
space, the bus width can be specified as
either 16 bits or 32 bits.
Rev. 4.00 Sep. 14, 2005 Page 285 of 982
Section 12 Bus State Controller (BSC)
REJ09B0023-0400