HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 894

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 23 I/O Ports
23.1.2
PADR is a 15-bit readable/writable register with one reserved bit that stores data for pins PTA14
to PTA0. PADR is initialized to H'0000 by a power-on reset, but it retains its previous value by a
manual reset, in standby mode or in sleep mode.
Rev. 4.00 Sep. 14, 2005 Page 844 of 982
REJ09B0023-0400
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Port A Data Register (PADR)
Bit Name

PA14DT
PA13DT
PA12DT
PA11DT
PA10DT
PA9DT
PA8DT
PA7DT
PA6DT
PA5DT
PA4DT
PA3DT
PA2DT
PA1DT
PA0DT
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Bits PA14DT to PA0DT correspond to pins PTA14 to
PTA0. When the pin function is general output port, the
value of the corresponding PADR bit in PADR is
returned directly by reading the port. When the function
is general input port, the corresponding pin level is read
by reading the port. Table 23.1 shows the function of
PADR.