HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 740

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.1
The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into
SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one
byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register.
The CPU cannot read or write to SCRSR directly.
19.3.2
The 16-byte receive FIFO data register (SCFRDR) stores serial receive data. The SCIF completes
the reception of one byte of serial data by moving the received data from the receive shift register
(SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored.
The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the
SCFRDR, the value is undefined. When this register is full of receive data, subsequent serial data
is lost.
SCFRDR is initialized to undefined value by a power-on reset.
19.3.3
The transmit shift register (SCTSR) transmits serial data. The SCIF loads transmit data from the
transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TxD
pin, LSB (bit 0) first. After transmitting one data byte, the SCIF automatically loads the next
transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or
write to SCTSR directly.
Rev. 4.00 Sep. 14, 2005 Page 690 of 982
REJ09B0023-0400
Bit
7 to 0
Receive Shift Register (SCRSR)
Receive FIFO Data Register (SCFRDR)
Transmit Shift Register (SCTSR)
Bit Name

Initial
value
Undefined R
R/W
Description
FIFO for transmits serial data