HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 130

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
Note:
Rev. 4.00 Sep. 14, 2005 Page 80 of 982
REJ09B0023-0400
Instruction
STC
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STS
STS
STS
STS.L
STS.L
STS.L
TRAPA
*
R7_BANK,Rn
SR,@–Rn
GBR,@–Rn
VBR,@–Rn
SSR,@–Rn
SPC,@–Rn
R0_BANK,
@–Rn
R1_BANK,
@–Rn
R2_BANK,
@–Rn
R3_BANK,
@–Rn
R4_BANK,
@–Rn
R5_BANK,
@–Rn
R6_BANK,
@–Rn
R7_BANK,
@–Rn
MACH,Rn
MACL,Rn
PR,Rn
MACH,@–Rn
MACL,@–Rn
PR,@–Rn
#imm
Number of states before the chip enters the sleep state.
The table shows the minimum number of clocks required for execution. In practice, the
number of execution cycles will be increased if there is contention between an
instruction fetch and a data access, or if the destination register of a load instruction
(memory → register) is also used by the following instruction.
Instruction Code
0000nnnn11110010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0100nnnn00110011
0100nnnn01000011
0100nnnn10000011
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Operation
R7_BANK→ Rn
Rn–4 → Rn, SR → (Rn)
Rn–4 → Rn, GBR → (Rn)
Rn–4 → Rn, VBR → (Rn)
Rn–4 → Rn, SSR → (Rn)
Rn–4 → Rn, SPC → (Rn)
Rn–4 → Rn, R0_BANK → (Rn)
Rn–4 → Rn, R1_BANK → (Rn)
Rn–4 → Rn, R2_BANK → (Rn)
Rn–4 → Rn, R3_BANK → (Rn)
Rn–4 → Rn, R4_BANK → (Rn)
Rn–4 → Rn, R5_BANK → (Rn)
Rn–4 → Rn, R6_BANK → (Rn)
Rn–4 → Rn, R7_BANK → (Rn)
MACH → Rn
MACL → Rn
PR → Rn
Rn–4 → Rn, MACH → (Rn)
Rn–4 → Rn, MACL → (Rn)
Rn–4 → Rn, PR → (Rn)
PC → SPC, SR → SSR,
imm << 2 → TRA,
VBR + H'0100 → PC
Execution
States
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
T Bit
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