HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 123

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Arithmetic Operation Instructions
Table 2.20 Arithmetic Operation Instructions
Instruction
ADD
ADD
ADDC
ADDV
CMP/EQ
CMP/EQ
CMP/HS
CMP/GE
CMP/HI
CMP/GT
CMP/PL
CMP/PZ
CMP/STR
DIV1
DIV0S
DIV0U
DMULS.L Rm,Rn
Rm,Rn
#imm,Rn
Rm,Rn
Rm,Rn
#imm,R0
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Instruction Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
0011nnnnmmmm0000
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010101
0100nnnn00010001
0010nnnnmmmm1100
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0011nnnnmmmm1101
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
If Rn = Rm, 1 → T
If Rn ≥ Rm with
unsigned data, 1 → T
If Rn ≥ Rm with signed data,
1 → T
If Rn > Rm with
unsigned data, 1 → T
If Rn > Rm with signed data,
1 → T
If Rn > 0, 1 → T
If Rn ≥ 0, 1 → T
If Rn and Rm have an
equivalent byte, 1 → T
Single-step division (Rn/Rm)
MSB of Rn → Q,
MSB of Rm → M, M ^ Q → T
0 → M/Q/T
Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
Rev. 4.00 Sep. 14, 2005 Page 73 of 982
Execution
States
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2(5) *
1
REJ09B0023-0400
Section 2 CPU
T Bit
—
—
Carry
Overflow
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
—