HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 139

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 2.30 Correspondence between DSP Instruction Operands and Registers
When writing parallel instructions, the B-field instruction is written first, followed by the A-field
instruction. A sample parallel processing program is shown in figure 2.16.
Square brackets mean that the contents can be omitted.
The no operation instructions NOPX and NOPY can be omitted. Table 2.31 gives an overview of
the B field in parallel operation instructions.
A semicolon is the instruction line delimiter, but this can also be omitted. If the semicolon
delimiter is used, the area to the right of the semicolon can be used as a comment field. This has
the same function as with conventional SH tools.
The DSR register condition code bit (DC) is always updated on the basis of the result of an
unconditional ALU or shift operation instruction. Conditional instructions do not update the DC
bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means
of bits CS0 to CS2 in the DSR register. The DC bit update rules are shown in table 2.32.
Register
A0
A1
M0
M1
X0
X1
Y0
Y1
DCF
PADD A0, M0, A0
PINC X1, A1
PCMP X1, M0
Sx
Yes
Yes
—
—
Yes
Yes
—
—
Figure 2.16 Sample Parallel Instruction Program
Sy
—
—
Yes
Yes
—
—
Yes
Yes
ALU/BPU Operations
PMULS X0, Y0, M0
Dz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
MOVX.W @R4+, X0
MOVX.W A0, @R5+R8
MOVX.W @R4
Du
Yes
Yes
—
—
Yes
—
Yes
—
Rev. 4.00 Sep. 14, 2005 Page 89 of 982
Se
—
Yes
—
—
Yes
Yes
Yes
—
Multiply Operations
MOVY.W @R6+, Y0 [;]
MOVY.W @R7+, Y0 [;]
[NOPY] [;]
Sf
—
Yes
—
—
Yes
—
Yes
Yes
REJ09B0023-0400
Section 2 CPU
Dg
Yes
Yes
Yes
Yes
—
—
—
—