HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 197

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Mode 2: The frequency of the signal received from the EXTAL pin or crystal resonator LSI is
quadrupled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency
required of the externally generated clock. Either a crystal resonator with a frequency in the range
from 10 to 12.5 MHz or an external signal in the same frequency range input on the EXTAL pin
may be used. The frequency range of CKIO is from 40 to 50 MHz.
Mode 6: The frequency of the signal received from the EXTAL pin or crystal resonator LSI is
doubled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency
required of the crystal resonator. A crystal resonator or an external signal with a frequency in the
range from 10 to 25 MHz may be used. The frequency range of CKIO is from 20 to 50 MHz.
Mode 7: In this mode, the CKIO pin functions as an input pin. An external clock signal is
supplied to this pin; after this signal is received, the PLL circuit 1 shapes its waveform and
multiplies its frequency. The resulting clock signal is then supplied within the LSI. For reduced
current and hence power consumption, pull up the EXTAL pin and open the XTAL pin when the
LSI is used in mode 7.
Table 4.3
Clock
operating
mode
2
6
FRQCR
register
setting
H'1001
H'1002
H'1003
H'1103
H'1113
H'1000
H'1001
H'1002
H'1003
H'1101
H'1103
H'1111
H'1113
H'1202
H'1222
Relationship between Clock Mode and Frequency Range
PLL
Circuit 1
ON (×1)
ON (×1)
ON (×1)
ON (×2)
ON (×2)
ON (×1)
ON (×1)
ON (×1)
ON (×1)
ON (×2)
ON (×2)
ON (×2)
ON (×2)
ON (×3)
ON (×3)
PLL frequency
multiplier
PLL
Circuit 2
ON (×4)
ON (×4)
ON (×4)
ON (×4)
ON (×4)
ON (×2)
ON (×2)
ON (×2)
ON (×2)
ON (×2)
ON (×2)
ON (×2)
ON (×2)
ON (×2)
ON (×2)
Ratio of internal
clock frequencies
(I:B:P)
4:4:2
4:4:4/3
4:4:1
8:4:2
4:4:2
2:2:2
2:2:1
2:2:2/3
2:2:1/2
4:2:2
4:2:1
2:2:2
2:2:1
6:2:2
2:2:2
Input clock
10 to 12.5
10 to 12.5
10 to 12.5
10 to 12.5
10 to 12.5
10 to 16.66
10 to 25
10 to 25
10 to 25
10 to 16.66
10 to 25
10 to 16.66
10 to 25
13.33 to 16.66 26.66 to 33.33 80 to 100
13.33 to 16.66 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33
Output clock
(CKIO pin)
40 to 50
40 to 50
40 to 50
40 to 50
40 to 50
20 to 33.33
20 to 50
20 to 50
20 to 50
20 to 33.33
20 to 50
20 to 33.33
20 to 50
Selectable frequency ranges (MHz)
Rev. 4.00 Sep. 14, 2005 Page 147 of 982
Section 4 Clock Pulse Generator (CPG)
Internal clock Bus clock
40 to 50
40 to 50
40 to 50
80 to 100
40 to 50
20 to 33.33
20 to 50
20 to 50
20 to 50
40 to 66.66
40 to 100
20 to 33.33
20 to 50
40 to 50
40 to 50
40 to 50
40 to 50
40 to 50
20 to 33.33
20 to 50
20 to 50
20 to 50
20 to 33.33
20 to 50
20 to 33.33
20 to 50
26.66 to 33.33 26.66 to 33.33
REJ09B0023-0400
Peripheral clock
20 to 25
13.33 to 16.66
10 to 12.5
20 to 25
20 to 25
20 to 33.33
10 to 25
6.66 to 16.66
5 to 12.5
20 to 33.33
10 to 25
20 to 33.33
10 to 25