HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 17

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 User Break Controller (UBC) ..........................................................241
11.1 Features.............................................................................................................................. 241
11.2 Register Descriptions ......................................................................................................... 243
11.3 Operation ........................................................................................................................... 256
11.4 Usage Notes ....................................................................................................................... 266
Section 12 Bus State Controller (BSC)..............................................................269
12.1 Features.............................................................................................................................. 269
12.2 Input/Output Pins ............................................................................................................... 272
12.3 Area Overview ................................................................................................................... 273
12.4 Register Descriptions ......................................................................................................... 277
10.6.2 Timing to Clear an Interrupt Source ..................................................................... 240
11.2.1 Break Address Register A (BARA) ...................................................................... 243
11.2.2 Break Address Mask Register A (BAMRA)......................................................... 244
11.2.3 Break Bus Cycle Register A (BBRA)................................................................... 244
11.2.4 Break Address Register B (BARB) ...................................................................... 246
11.2.5 Break Address Mask Register B (BAMRB) ......................................................... 247
11.2.6 Break Data Register B (BDRB) ............................................................................ 247
11.2.7 Break Data Mask Register B (BDMRB)............................................................... 248
11.2.8 Break Bus Cycle Register B (BBRB) ................................................................... 249
11.2.9 Break Control Register (BRCR) ........................................................................... 251
11.2.10 Execution Times Break Register (BETR)............................................................. 254
11.2.11 Branch Source Register (BRSR)........................................................................... 254
11.2.12 Branch Destination Register (BRDR)................................................................... 255
11.3.1 Flow of the User Break Operation ........................................................................ 256
11.3.2 Break on Instruction Fetch Cycle.......................................................................... 257
11.3.3 Break on Data Access Cycle................................................................................. 258
11.3.4 Break on X/Y-Memory Bus Cycle........................................................................ 259
11.3.5 Sequential Break ................................................................................................... 260
11.3.6 Value of Saved Program Counter ......................................................................... 260
11.3.7 PC Trace ............................................................................................................... 261
11.3.8 Usage Examples.................................................................................................... 262
12.3.1 Area Division........................................................................................................ 273
12.3.2 Shadow Area......................................................................................................... 274
12.3.3 Address Map ......................................................................................................... 275
12.3.4 Area 0 Memory Type and Memory Bus Width .................................................... 277
12.4.1 Common Control Register (CMNCR) .................................................................. 278
12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) ..... 281
12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)... 286
Rev. 4.00 Sep. 14, 2005 Page xvii of l