HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 448

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
(2) Transfer from the SDRAM interface to the external device with DACK
Notes:
Rev. 4.00 Sep. 14, 2005 Page 398 of 982
REJ09B0023-0400
CS3BCR Idle Setting
0
0
0
0
1
1
1
1
2
2
2
2
4
4
4
4
n (n>=6)
1. For single transfer from the external device with DACK to the SDRAM interface, the
2. Minimum number of idle cycles for other than the above cases.
DMAC is operated by Bφ. The minimum number of idle cycles is not affected by
changing a clock ratio.
minimum number of idle cycles is not affected by the IWW, IWRWD, IWRWS, IWRRD,
and IWRRS bits in CSnBCR.
For CMNCR.DMIWA = 0, the setting is identical to CMNCR.DMAIW[1:0] in (1) in the
above table.
BSC Register Setting*
CS3WCR.WTRP Setting
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3

2
Minimum Number of
Idle Cycles
3
3
3
4
3
3
3
4
3
3
3
4
5
5
5
5
n+1