HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 409

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

When bank active mode is set, if only accesses to the respective banks in the area 3 space are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 12.23 or 12.26, followed by repetition of the cycle in figure 12.24 or 12.27. An
access to a different area during this time has no effect. If there is an access to a different row
address in the bank active state, after this is detected the bus cycle in figure 12.24 or 12.27 is
executed instead of that in figure 12.25 or 12.28. In bank active mode, too, all banks become
inactive after a refresh cycle or after the bus is released as the result of bus arbitration.
Figure 12.23 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1)
RASL, RASU
CASL, CASU
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
CSn
BS
1
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tr
Tc1
Td1
Tc2
Td2
Tc3
Td3
Tc4
Rev. 4.00 Sep. 14, 2005 Page 359 of 982
Section 12 Bus State Controller (BSC)
Td4
Tde
REJ09B0023-0400