HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 156

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 3 DSP Operation
Table 3.4
Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR
register are basically updated in accordance with the operation result. In case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of the DC bit is selected by the CS0 to CS2 (condition selection)
bits in DSR. The DC bit result is:
1. Carry or Borrow Mode: CS[2:0] = 000
2. Negative Value Mode: CS[2:0] = 001
3. Zero Value Mode: CS[2:0] = 010
4. Overflow Mode: CS[2:0] = 011
Rev. 4.00 Sep. 14, 2005 Page 106 of 982
REJ09B0023-0400
Mnemonic
PAND
POR
PXOR
The DC bit is always cleared.
Bit 31 of the operation result is loaded into the DC bit.
The DC bit is set when the operation result is zero; otherwise it is cleared.
The DC bit is always cleared.
Variation of ALU Logical Operations
39
Guard
Ignored
Cleared
Function
Logical AND
Logical OR
Logical exclusive OR
31
Soruce 1
Figure 3.7 ALU Logical Operation Flow
39
Guard
31
Destination
0
ALU
Source 1
Sx
Sx
Sx
39
Guard
31
Source 2
0
GT
Source 2
Sy
Sy
Sy
Z
DSR
N
V
0
DC
Destination
Dz
Dz
Dz