HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 52

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 1 Overview
Rev. 4.00 Sep. 14, 2005 Page 2 of 828
REJ09B0023-0400
Items
DSP
Clock pulse
generator (CPG)
Watchdog timer
Specification
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Mixture of 16-bit and 32-bit instructions
32-/40-bit internal data paths
Multiplier, ALU, barrel shifter and DSP register
Large DSP data registers
 Six 32-bit data registers
 Two 40-bit data registers
Extended Harvard Architecture for DSP data bus
 Two data buses
 One instruction bus
Max. four parallel operations: ALU, multiply, and two load or store
Two addressing units to generate addresses for two memory access
DSP data addressing modes: increment, indexing (with or without
modulo addressing)
Zero-overhead repeat loop control
Conditional execution instructions
Clock mode: Input clock can be selected from external input (EXTAL
or CKIO) or crystal oscillator
Three types of clocks generated:
 CPU clock: maximum 100 MHz
 Bus clock: maximum 50 MHz
 Peripheral clock: maximum 33 MHz
Power-down modes:
 Sleep mode
 Standby mode
 Module standby mode
Three types of clock modes (selectable PLL2 × 2 / × 4, clock / crystal
On-chip one-channel watchdog timer
Select from operation in watchdog-timer or interval-timer mode.
Interrupt generation is supported for the interval-timer mode.
oscillator)