HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 456

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Direct Memory Access Controller (DMAC)
• Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND
Figure 13.1 shows the block diagram of the DMAC.
Rev. 4.00 Sep. 14, 2005 Page 406 of 982
REJ09B0023-0400
can be set independently.
DREQ0 , DREQ1
(with acknowledge-
DACK0, DACK1
(memory mapped)
[Legend]
SAR_n:
DAR_n:
DMATCR_n:
CHCR_n:
DMAOR:
DMARS0,1:
DEIn:
n:
External ROM
External RAM
External device
External device
X/Y memory
peripheral module
DMA transfer acknowledge signal
ment)
On-chip
Interrupt controller
DMA transfer request signal
TEND
DMA source address register
DMA destination address register
DMA transfer count register
DMA channel control register
DMA operation register
DMA extension resource selector
DMA transfer end interrupt request to the CPU
0, 1, 2, 3
Figure 13.1 Block Diagram of the DMAC
Bus state
controller
DEIn
interface
Register
Request
Iteration
Start-up
control
control
control
priority
control
Bus
DMAC module
DMATCR_n
DMARS0,1
CHCR_n
DMAOR
SAR_n
DAR_n