HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 15

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

6.2
6.3
Section 7 Cache .................................................................................................179
7.1
7.2
7.3
7.4
Section 8 X/Y Memory......................................................................................193
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Section 9 Exception Handling ...........................................................................197
9.1
Register Descriptions ......................................................................................................... 166
6.2.1
6.2.2
6.2.3
6.2.4
Operation ........................................................................................................................... 171
6.3.1
6.3.2
6.3.3
6.3.4
Features.............................................................................................................................. 179
7.1.1
Register Descriptions ......................................................................................................... 182
7.2.1
7.2.2
Cache Operation................................................................................................................. 186
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
Memory-Mapped Cache .................................................................................................... 190
7.4.1
7.4.2
7.4.3
Features.............................................................................................................................. 193
X/Y Memory Access from CPU ........................................................................................ 194
X/Y Memory Access from DSP......................................................................................... 194
X/Y Memory Access from DMAC .................................................................................... 195
Usage Note......................................................................................................................... 195
Sleep Mode ........................................................................................................................ 195
Address Error ..................................................................................................................... 195
Register Descriptions ......................................................................................................... 198
Standby Control Register (STBCR)...................................................................... 166
Standby Control Register 2 (STBCR2)................................................................. 167
Standby Control Register 3 (STBCR3)................................................................. 168
Standby Control Register 4 (STBCR4)................................................................. 170
Sleep Mode ........................................................................................................... 171
Standby Mode ....................................................................................................... 172
Module Standby Function..................................................................................... 174
STATUS Pin Change Timings.............................................................................. 174
Cache Structure..................................................................................................... 180
Cache Control Register 1 (CCR1) ........................................................................ 182
Cache Control Register 2 (CCR2) ........................................................................ 183
Searching Cache ................................................................................................... 186
Read Access.......................................................................................................... 188
Prefetch Operation ................................................................................................ 188
Write Access ......................................................................................................... 188
Write-Back Buffer ................................................................................................ 189
Coherency of Cache and External Memory .......................................................... 189
Address Array ....................................................................................................... 190
Data Array ............................................................................................................ 190
Usage Examples.................................................................................................... 192
Rev. 4.00 Sep. 14, 2005 Page xv of l