HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 561

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

17.2.2
CMCSR is a 16-bit register that indicates compare match generation, enables interrupts or DMA
transfer requests, and selects the counter input clock.
CMCSR is initialized to H'0000 by a power on reset, but is not initialized in standby mode.
Bit
15 to 8
7
6
5
4
3, 2
Compare Match Timer Control/Status Register (CMCSR)
Bit Name

CMF

CMR1
CMR0

Initial
value
All 0
0
0
0
0
All 0
R/W
R
R/(W)* Compare Match Flag
R
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match
[Clearing condition]
When 0 is written to CMF after reading CMF = 1
1: CMCNT and CMCOR values match
Reserved
This bit is always read as 0. The write value should
always be 0.
Compare Match Request
These bits enable or disable DMA transfer request or
interrupt request generation when a compare match
occurs.
00: DMA transfer request/interrupt request disabled
01: DMA transfer request enabled
10: Interrupt request enabled
11: Reserved (Setting prohibited)
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Sep. 14, 2005 Page 511 of 982
Section 17 Compare Match Timer (CMT)
REJ09B0023-0400