HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 349

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

• CS6BWCR
Bit
1
0
Bit
31 to 21
20
19 to 13
12
11
Bit Name
HW1
HW0
Bit Name

BAS

SW1
SW0
Initial
Value
0
0
Initial
Value
All 0
0
All 0
0
0
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R/W
Description
Delay Cycles from RD, WEn Negation to Address,
CSn Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Byte-Selection SRAM Byte Access Selection
Specifies the WEn and RD/WR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read timing and
1: Asserts the WEn signal during the read/write access
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Delay Cycles from Address, CSn Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address, CSn
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
asserts the RD/WR signal during the write access
cycle.
cycle and asserts the RD/WR signal at the write
timing.
Rev. 4.00 Sep. 14, 2005 Page 299 of 982
Section 12 Bus State Controller (BSC)
REJ09B0023-0400