HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 478

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request: In this mode, the transfer is performed in response to the
DMA transfer request signal of an on-chip peripheral module. Signals that request DMA transfer
include A/D conversion-completed transfer requests from A/D converter 0, compare-match
transfer requests from the CMT0 timer, transmit-data empty transfer requests and receive-data full
transfer requests from the SCIF0 to SCIF2 that are set by DMARS0 and 1, compare-match and
input-capture interrupts from the MTU0 to MTU4 timers, transmit-data-empty transfer requests
and receive-data-full transfer requests from the USB module, A/D conversion-completed transfer
requests from A/D converter 1, and compare-match transfer requests from the CMT1 timer.
When the transfer request is a transmit-data-empty transfer request, set the transfer destination as
the corresponding SCIF transmit-data register. Likewise, when the transfer request is a receive-
data full transfer request, set the transfer destination as the corresponding SCIF receive-data
register. Requests from the USB are handled in an analogous way. If a transfer is requested from
the A/D converter 0 and A/D converter 1, the transfer source must be the A/D data register
(ADDR). Any address can be specified for data source and destination, when transfer request is
generated by CMT0, CMT1, and MTU0 to MTU4.
Table 13.7 Selecting On-Chip Peripheral Module Request Modes with the RS3 to RS0 Bits
Rev. 4.00 Sep. 14, 2005 Page 428 of 982
REJ09B0023-0400
CHCR
RS[3:0]
1110
1111
1000
MID
Any
Any
100010 00
100100 00
010000 00
DMARS
RID
Any A/D converter 0 ADI (A/D conversion
Any CMT0
01
01
01
DMA Transfer
Request
Source
SCIF0
transmitter
SCIF0 receiver RXI (receive data FIFO
SCIF1
transmitter
SCIF1 receiver RXI (receive data FIFO
SCIF2
transmitter
SCIF2 receiver RXI (receive data FIFO
DMA Transfer
Request Signal
end interrupt)
Compare-match transfer
request
TXI (transmit data FIFO
empty interrupt)
full interrupt)
TXI (transmit data FIFO
empty interrupt)
full interrupt)
TXI (transmit data FIFO
empty interrupt)
full interrupt)
Source
ADDR
Any
Any
SCFRDR0 Any
Any
SCFRDR1 Any
Any
SCFRDR2 Any
Destination Bus Mode
Any
Any
SCFTDR0
SCFTDR1
SCFTDR2
Cycle steal
Burst/
cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal