HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 81

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

2.1.2
This LSI has 8 control registers: SR, SSR, SPC, GBR, VBR, RS, RE, and MOD (figure 2.5). SSR,
SPC, GBR and VBR are the same as the SH-3 registers. The DSP mode is activated only when
SR.DSP = 1.
Repeat start register RS, repeat end register RE, and repeat counter RC (12-bit part of SR) and
repeat control bits RF0 and RF1 are new registers and control bits which are used for repeat
control. Modulo register MOD and modulo control bits DMX and DMY in SR are also new
register and control bits.
In SR, there are six additional control bits: RC11 to RC0, RF0, RF1, DMX, DMY and DSP. DMX
and DMY are used for modulo addressing control. If DMX is 1, the modulo addressing mode is
effective for the X memory address pointer, Ax (R4 or R5). If DMY is 1, the modulo addressing
mode is effective for the Y memory address pointer, Ay (R6 or R7). However, both X and Y
address pointers cannot be operated in modulo addressing mode even though both DMX and
DMY bits are set. The case where DMX = DMY = 1 is reserved for future expansion. If both
DMX and DMY are set simultaneously, the hardware will provisionally treat only the Y address
pointer as the modulo addressing mode pointer. Modulo addressing is available for X and Y data
transfer operations (MOVX and MOVY), but not for a single data transfer operation (MOVS).
RF1 and RF0 hold information on the number of repeat steps, and are set when a SETRC
instruction is executed. When RF1 and RF0 = 00, the current repeat module consists of one
instruction step. RF1 and RF0 = 01 means two instruction steps, RF1 and RF0 = 11 means three
instruction steps, and RF1 and RF0 = 10 means the current repeat module consists of four or more
instructions.
Although RC11 to RC0 and RF1 and RF0 can be changed by a store/load to SR, use of the
dedicated manipulation instruction SETRC is recommended.
SR also has a 12-bit repeat counter, RC, which is used for efficient loop control. The repeat start
register (RS) and repeat end register (RE) are also provided for loop control. They hold the start
Is:
Ay1:
Iy:
As0:
As1:
As2:
As3:
Control Registers
.REG
.REG
.REG
.REG
.REG
.REG
.REG
(R7)
(R9)
(R4)
(R5)
(R2)
(R3)
(R8)
; This is optional, if another alias is required for single data transfer.
; This is optional, if another alias is required for single data transfer.
; This is optional, if another alias is required for single data transfer.
Rev. 4.00 Sep. 14, 2005 Page 31 of 982
REJ09B0023-0400
Section 2 CPU