HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 163

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated, even though the specified condition is true, and the operation is executed. In case of an
unconditional operation, they are always updated with the operation result.
The definition of the DC bit is selected by the CS0 to CS2 (condition selection) bits in DSR. The
DC bit result is:
1. Carry or Borrow Mode: CS[2:0] = 000
2. Negative Value Mode: CS[2:0] = 001
3. Zero Value Mode: CS[2:0] = 010
4. Overflow Mode: CS[2:0] = 011
5. Signed Greater Than Mode: CS[2:0] = 100
6. Signed Greater Than or Equal Mode: CS[2:0] = 101
The DC bit is always cleared.
The DC bit is set when the operation result is a negative value, and cleared when the operation
result is zero or a positive value.
The DC bit is set when the operation result is zero; otherwise it is cleared.
The DC bit is always cleared.
The DC bit is set when the operation result is a positive value; otherwise it is cleared.
The DC bit is set when the operation result is zero or a positive value; otherwise it is cleared.
39
39
Guard
Guard
31
31
Figure 3.11 PDMSB Operation Flow
Destination
Priority encoder
Source 1 or 2
0
0
GT
Cleared
Rev. 4.00 Sep. 14, 2005 Page 113 of 982
Z
DSR
N
V
DC
Section 3 DSP Operation
REJ09B0023-0400