HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 157

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

5. Signed Greater Than Mode: CS[2:0] = 100
6. Signed Greater Than or Equal Mode: CS[2:0] = 101
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
3.1.4
Figure 3.8 shows the multiply operation flow. Table 3.5 shows the variation of this type of
operation and table 3.6 shows the correspondence between each operand and registers. The
multiply operation of the DSP unit is single-word signed single-precision multiplication. These
operations are executed in the DSP stage, as shown in figure 3.2. The DSP stage is the same stage
as the MA stage in which memory access is performed.
If a double-precision multiply operation is needed, the SH-3's standard double-word multiply
instructions can be made of use.
The DC bit is always cleared.
The DC bit is always cleared.
Fixed-Point Multiply Operation
Ignored
39
Guard
Figure 3.8 Fixed-Point Multiply Operation Flow
31
S
0
Source 1
39
Guard
31
S
MAC
Destination
0
39
Guard
1 0
0
31
S
Rev. 4.00 Sep. 14, 2005 Page 107 of 982
Source 2
Section 3 DSP Operation
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