HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 40

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25 Electrical Characteristics
Figure 25.1 Power-On Sequence ................................................................................................ 908
Figure 25.2 EXTAL Clock Input Timing ................................................................................... 917
Figure 25.3 CKIO Clock Input Timing ...................................................................................... 917
Figure 25.4 CKIO and CKIO2 Clock Input Timing ................................................................... 917
Figure 25.5 Oscillation Settling Timing (Power-On) ................................................................. 918
Figure 25.6 Phase Difference between CKIO and CKIO2 ......................................................... 918
Figure 25.7 Oscillation Settling Timing (Standby Mode Canceled by Reset)............................ 918
Figure 25.8 Oscillation Settling Timing (Standby Mode Canceled by NMI or IRQ)................. 919
Figure 25.9 Reset Input Timing.................................................................................................. 921
Figure 25.10 Interrupt Input Timing........................................................................................... 921
Figure 25.11 Bus Release Timing .............................................................................................. 922
Figure 25.12 Pin Driving Timing in Standby Mode ................................................................... 922
Figure 25.13 Basic Bus Timing for Normal Space (No Wait).................................................... 925
Figure 25.14 Basic Bus Timing for Normal Space (Software 1 Wait) ....................................... 926
Figure 25.15 Basic Bus Timing for Normal Space (One Cycle of Externally Input/
Figure 25.16 Basic Bus Timing for Normal Space (One Cycle of Externally Input/
Figure 25.17 Basic Bus Timing for Normal Space (One Cycle of Software Wait,
Figure 25.18 MPX-IO Interface Bus Cycle (Three Address Cycles,
Figure 25.19 Burst MPX-IO Interface Bus Cycle Single Read Write
Figure 25.20 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One
Figure 25.21 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One
Figure 25.22 Burst ROM Read Cycle (One Software Wait Cycle, One Asynchronous
Figure 25.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge,
Figure 25.24 Synchronous DRAM Single Read Bus Cycle (Auto Precharge,
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
Figure 25.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
Rev. 4.00 Sep. 14, 2005 Page xl of l
WAITSEL = 0) ..................................................................................................... 927
WAITSEL = 1) ..................................................................................................... 928
External Wait Cycle Valid (WM Bit = 0), No Idle Cycle).................................... 929
One Software Wait Cycle, One External Wait Cycle) .......................................... 930
(One Address Cycle, One Software Wait) ............................................................ 931
Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control)) .... 932
Asynchronous External Wait Cycle, BAS = 1 (Write Cycle WE Control)).......... 933
External Burst Wait Cycle, Two Burst) ................................................................ 934
CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle) ...................................... 935
CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle) ...................................... 936
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle) .......... 937
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle) .......... 938