HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 44

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 2.31
Table 2.32
Table 2.33
Section 3 DSP Operation
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Table 3.12
Table 3.13
Table 3.14
Table 3.15
Table 3.16
Table 3.17
Table 3.18
Section 4 Clock Pulse Generator (CPG)
Table 4.1
Table 4.2
Table 4.3
Section 6 Power-Down Modes
Table 6.1
Table 6.2
Table 6.3
Section 7 Cache
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Rev. 4.00 Sep. 14, 2005 Page xliv of l
DSP Operation Instructions .................................................................................... 90
DC Bit Update Definitions ..................................................................................... 96
Examples of NOPX and NOPY Instruction Codes................................................. 98
Variation of ALU Fixed-Point Operations............................................................ 100
Correspondence between Operands and Registers ............................................... 100
Variation of ALU Integer Operations ................................................................... 104
Variation of ALU Logical Operations .................................................................. 106
Variation of Fixed-Point Multiply Operation ....................................................... 108
Correspondence between Operands and Registers ............................................... 108
Variation of Shift Operations................................................................................ 109
Operation Definition of PDMSB .......................................................................... 114
Variation of PDMSB Operation............................................................................ 115
Variation of Rounding Operation ......................................................................... 116
Definition of Overflow Protection for Fixed-Point Arithmetic Operations .......... 117
Definition of Overflow Protection for Integer Arithmetic Operations.................. 117
Variation of Local Data Move Operations............................................................ 122
Correspondence between Operands and Registers ............................................... 123
Address Value to be Stored into SPC (1).............................................................. 125
Address Value to be Stored into SPC (2).............................................................. 126
RS and RE Setting Rule........................................................................................ 128
Summary of DSP Data Transfer Instructions ....................................................... 133
Pin Configuration and Functions of the Clock Pulse Generator ........................... 146
Clock Operating Modes ........................................................................................ 146
Relationship between Clock Mode and Frequency Range.................................... 147
States of Power-Down Modes .............................................................................. 164
Pin Configuration.................................................................................................. 165
Register States in Standby Mode .......................................................................... 172
Cache Specifications............................................................................................. 179
Address Space Subdivisions and Cache Operation............................................... 179
LRU and Way Replacement ................................................................................. 181
Way to be Replaced when a Cache Miss Occurs in PREF Instruction ................. 185
Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction .. 185
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 0)............... 185
LRU and Way Replacement (when W2LOCK = 0 and W3LOCK = 1)............... 186