HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 340

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
• CS4WCR
Rev. 4.00 Sep. 14, 2005 Page 290 of 982
REJ09B0023-0400
Bit
31 to 21
20
19
18
17
16
15 to 13
Bit Name

BAS

WW2
WW1
WW0

Initial
Value
All 0
0
0
0
0
0
All 0
R/W
R
R/W
R
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Byte-Selection SRAM Byte Access Selection
Specifies the WEn and RD/WR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read timing and
1: Asserts the WEn signal during the read access cycle
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
Reserved
These bits are always read as 0. The write value
should always be 0.
000: The same cycles as WR[3:0] setting (number of
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
asserts the RD/WR signal during the write access
cycle.
and asserts the RD/WR signal at the write timing.
read access wait cycles)