HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 69

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Classification
Clock
Operating mode
control
System control
Interrupts
Address bus
Data bus
Bus control
CKIO
CKIO2
MD3, MD2,
MD0
RESETP
RESETM
STATUS1,
STATUS0
BREQ
BACK
NMI
IRQ7 to IRQ0 I
CS0,
CS2 to CS4,
CS5A, CS5B,
CS6A, CS6B
RD
Symbol
A25 to A0
D31 to D0
I/O
O
O
I
I
I
O
I
O
I
O
I/O
O
O
Name
System clock
System clock
Mode set
Power-on reset
Manual reset
Status output
Bus-mastership
Bus-mastership
Non-maskable
Interrupt requests
7 to 0
Chip select 0,
Read
request
request
acknowledge
interrupt
Address bus
Data bus
2 to 4, 5A, 5B,
6A, 6B
Function
Supplies the system clock to external
devices.
Supplies the system clock to external
devices.
Sets the operating mode. Do not
change values on these pins during
operation.
MD2, MD0 set the clock mode, MD3
set the bus-width mode of area 0.
When low, this LSI enters the power-
on reset state.
When low, this LSI enters the
manual reset state.
Indicate that this LSI is in software
standby, reset, or sleep mode.
Low when an external device
requests the release of the bus
mastership.
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Non-maskable interrupt request pin.
Fix to high level when not in use.
Maskable interrupt request pin.
Selectable as level input or edge
input. The rising edge, falling edge,
and both edges are selectable as
edges.
Outputs addresses.
32-bit bidirectional bus.
Chip-select signal for external
memory or devices.
Indicates reading of data from
external devices.
Rev. 4.00 Sep. 14, 2005 Page 19 of 982
Section 1 Overview
REJ09B0023-0400